The present disclosure relates to a method of enabling large feature alignment marks with sidewall image transfer patterning.
Semiconductor manufacturing utilizes the sequential patterning of process layers on a single semiconductor wafer. Lithographic exposure tools known as steppers or scanners print multiple integrated circuit patterns or fields (also known as product cells) by lithographic methods on successive layers of the wafer. These exposure tools transfer patterns of a photo mask having customized circuit patterns to thin films formed on a wafer. In doing so, different layers are patterned by applying step and repeat lithographic exposure or step and scan lithographic exposure, in which the full area of the wafer is patterned by sequential exposure of the stepper fields containing one or more integrated circuits.
The image transfer process comprises steps of forming a photoresist layer on a non-process layer, illuminating the photoresist layer through a photo mask having the customized circuit patterns, developing the photoresist layer and then etching the non-process layer by using the patterned photoresist layer as a mask to accomplish the image transfer process. This image transfer process is performed several times to transfer the circuit patterns to each non-process layer to form the integrated circuit device. Typically, 20 to 50 layers are required to create an integrated circuit.
In order to match corresponding features in successive lithographic process layers on the semiconductor wafer, it is important to keep both alignment and overlay errors as small as possible and within predetermined limits. Measurements are typically performed using metrology imaging tools, such as optical, scanning e-beam or atomic force microscopy systems. In practice, alignment and overlay metrology systems often require different specialized target designs and locations on each layer.
Overlay targets can be comprised of sub-patterns from both the same and different masks. The images are analyzed to determine the relative layer-to-layer and within-layer placement of the sub-patterns among the various mask layers printed on the wafer. Overlay error is the deviation of the relative position among patterns from their designed relative positions, as determined by an overlay metrology tool. In doing so, the overlay correlation set in an exposure tool is used to insure alignment precision between the successively patterned layers. A metrology process determines precision of the overlay alignment by referring to the overlay alignment mark sets of the successive patterned layers.
To ensure circuit functionality, overlay errors must be minimized among all wafer patterns, consistent with the ground rules of the most critical circuit devices. While prior art has focused on several metrology processes for determining overlay alignment, as semiconductor device critical dimensions continue to shrink, and the speed and functionality requirements thereof continue to increase, improvements continue to be needed in minimizing alignment and overlay errors.
That is, a need exists in the art for methods, apparatus, and structures that align successively patterned layers to reduce misalignment errors as critical dimensions of semiconductor devices continue to shrink and the processing requirements thereof continue to develop.